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QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FEATURES:
* * * * * * * * * * * * 5V operation Low noise TTL level outputs < 350ps output skew, Q0-Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to Motorola MC88915 Positive or negative edge synchronization (PE) Balanced drive outputs 24mA 160MHz maximum frequency (2xQ output) Available in QSOP and PLCC packages
QS5919T
DESCRIPTION
The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure < 350ps skew between the Q0-Q4, and Q/2 outputs. The QS5919T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5919T is designed for use in highperformance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL LO CK SYNC0 SYNC1 O E/RST
0 0 1 PH A S E D ETEC TO R LO O P FIL TER 1
PE
FEE DBACK
PLL_E N
FREQ _SEL
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q /2
Q5
Q4
Q3
Q2
Q1
Q0
2xQ
INDUSTRIAL TEMPERATURE RANGE
1
c 2000 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-5815/-
QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND Q5 VDD OE/RST FEEDBACK REF_SEL SYNC0 AVDD PE AGND SYNC1 FREQ_SEL GND Q0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SO28-9 21 20 19 18 17 16 15 28 27 26 25 24 23 22 Q4 VDD 2xQ Q/2 GND Q3 VDD Q2 GND
AGND FEEDBACK REF_SEL SYNC0 AVDD PE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 J28-1
OE/RST
GND
4
3
2
1
28
Q4
27
26 25 24 23 22 21 20 19 Q/2 GND Q3 VDD Q2 GND LOCK
LOCK PLL_EN GND Q1 VDD
FREQ_SEL
SYNC1
GND
GND
VDD
Q1
QSOP TOP VIEW
PLCC TOP VIEW
(1)
Unit V V
ABSOLUTE MAXIMUM RATINGS
Symbol VDD, AVDD VIN Rating Supply Voltage to Ground DC Input Voltage VIN Maximum Power QSOP Dissipation (TA = 85C) PLCC Storage Temperature Range Max. -0.5 to +7 -0.5 to +7
TSTG
655 mW 770 mW -65C to +150C C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25 C, f = 1MHz, VIN = 0V)
QSOP Parameter CIN Typ. 3 Max. 4 Typ. 4 PLCC Max. 6 Unit pF
2
PLL_EN
Q0
2xQ
VDD
Q5
VDD
QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name SYNC0 SYNC1 REF_SEL FREQ_SEL FEEDBACK Q0 -Q4 Q5 2xQ Q/2 LOCK OE/RST PLL_EN PE VDD AVDD GND AGND I/O I I I I I O O O O O I I I -- -- -- -- Reference clock input Reference clock input Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0. VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency relationships. See the Frequency Selection Table for more information. Clock outputs Clock output. Matched in frequency, but inverted with respect to Q. Clock output. Matched in phase, but frequency is double the Q frequency. Clock output. Matched in phase, but frequency is half the Q frequency. PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to the inputs. Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are enabled. PLL enable. Enables and disables the PLL. Useful for testing purposes. When PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the negative edge of SYNC. Power supply for output buffers. Power supply for phase lock loop and other internal circuitries. Ground supply for output buffers. Ground supply for phase lock loop and other internal circuitries. Description
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = -40C to +85C, AVDD / VDD = 5.0V 10%
Symbol FMAX_2XQ FMAX_Q FMAX_Q/2 FMIN_2XQ FMIN_Q FMIN_Q/2 Description Max Frequency, 2xQ Max Frequency, Q0 - Q4, Q5 Max Frequency, Q/2 Min Frequency, 2xQ Min Frequency, Q0 - Q4, Q5 Min Frequency, Q/2 - 55 55 27.5 13.75 20 10 5 - 70 70 35 17.5 20 10 5 - 100 100 50 25 20 10 5 - 133 133 66.5 33.25 20 10 5 - 160 160 80 40 20 10 5 Units MHz MHz MHz MHz MHz MHz
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QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
FREQ_SEL HIGH HIGH HIGH HIGH LOW LOW LOW LOW Output Used for Feedback Q/2 Q0 -Q4 Q5 2xQ Q/2 Q0 -Q4 Q5 2xQ SYNC (MHz) (allowable range) (1) Min. Max FMIN_Q/2 FMIN_Q FMIN_Q FMIN_2XQ FMIN_Q/2 /2 FMIN_Q /2 FMIN_Q /2 FMIN_2XQ /2 FMAX _Q/2 FMAX _Q FMAX _Q FMAX _2XQ FMAX _Q/2 /2 FMAX _Q /2 FMAX _Q /2 FMAX _2XQ /2 Q/2 SYNC SYNC / 2 - SYNC / 2 SYNC / 4 SYNC SYNC / 2 - SYNC / 2 SYNC / 4 Output Frequency Relationships (2) Q5 Q0 - Q4 - SYNC X 2 - SYNC SYNC - SYNC / 2 - SYNC X 2 - SYNC SYNC - SYNC / 2 SYNC X 2 SYNC - SYNC SYNC / 2 SYNC X 2 SYNC - SYNC SYNC / 2 2XQ SYNC X 4 SYNC X 2 - SYNC X 2 SYNC SYNC X 4 SYNC X 2 - SYNC X 2 SYNC
NOTES: 1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to FMAX_2XQ. Operation with Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies. 2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, AVDD / VDD = 5.0V 10%
Symbol VIH VIL VOH VOL VH IOZ IIN IPD Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Hysteresis Output Leakage Current Input Leakage Current Input Pull-Down Current (PE) Conditions Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VDD = Min., IOH = -24mA VDD = Min., IOH = -100A VDD = Min., IOL = 24mA VDD = Min., IOL = 100A -- VOUT = VDD or GND, VDD = Max. VIN = AVDD or GND, AVDD = Max. AVDD = Max., VIN = AVDD Min. 2 -- 2.4 3 -- -- -- -- -- -- Typ. -- -- -- -- -- -- 100 -- -- -- Max. -- 0.8 -- -- 0.45 0.2 -- 5 5 100 Unit V V V V V V mV A A A
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDD IDDD Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current
(1)
Test Conditions VDD = Max., OE/RST = LOW, SYNC = LOW, All outputs unloaded VDD = Max., VIN = 3.4V VDD = Max., CL = 0pF
Typ.
Max. 1.5 1.5 0.4
Unit mA mA mA/MHz
0.5 0.2
NOTE: 1. Relative to the frequency of Q outputs.
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QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
Symbol tR, tF FI tPWC DH Description (1) Maximum input rise and fall times, 0.8V to 2V Input Clock Frequency, SYNC0, SYNC1 (1) Input clock pulse, HIGH or LOW (2) Input duty cycle (2) Min. -- 2.5 2 25 Max. 3 FMAX _2XQ -- 75 Unit ns MHz ns %
NOTES: 1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL combinations. 2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tSKR tSKF tSKALL tPW tPW tJ tPD tLOCK tPZH tPZL tPHZ tPLZ tR, tF Parameter (1) Output Skew Between Rising Edges, Q0-Q4 and Q/2 (2) Output Skew Between Falling Edges, Q0-Q4 and Q/2 (2) Output Skew, All Outputs
(2,5)
Min. -- -- -- TCY/2 - 0.4 TCY/2 - 0.4 - 0.15 - 500 -- 0 0 0.3
Max. 350 350 500 TCY/2 + 0.4 TCY/2 + 0.4 0.15 0 10 7 6 1.5
Unit ps ps ps ns ns ns ps ms ns ns ns
Pulse Width, 2xQ output, >40MHz Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz Cycle-to-Cycle Jitter (4) SYNC Input to Feedback Delay SYNC to Phase Lock Output Enable Time, OE/RST LOW to HIGH (3) Output Enable Time, OE/RST HIGH to LOW (3) Output Rise/Fall Times, 0.8V 2V
(6)
NOTES: 1. See Test Loads and Waveforms for test load and termination. Test circuit 1 is used for output enable/disable parameters. Test circuit 2 is used for all other timing parameters. 2. Skew specifications apply under identical environments (loading, temperature, VCC, device speed grade). 3. Measured in open loop mode PLL_EN = 0. 4. Jitter is characterized with Q output at 20MHz. See FREQUENCY SELECTION TABLE for information on proper FREQ_SEL level for specified input frequencies. 5. Skew measured at selected synchronization edge. 6. tPD measured at device inputs at 1.5V, Q output at 80MHz.
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QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
AC TEST LOADS AND WAVEFORMS
VDD
300 7.0V O UTPUT 160
O UTPUT 300 68
30pF
20pF
TEST CIRCUIT 1
TEST CIRCUIT 2
1.0ns
1.0ns
tR
tF
3.0V 2.0V Vth = 1.5V 0.8V 0V 2.0V 1.5V 0.8V 0V tPW
TTL INPUT TEST WAVEFORM
EN A BLE DISABLE
TTL OUTPUT WAVEFORM
3V 1.5V CO NTRO L IN PU T tPZL O UTPUT NO R M ALLY LO W SW ITCH CLO SED 1.5V 0.3V tPZ H SW ITCH O UTPUT NO R M ALLY HIGH O PEN 1.5V tPHZ 0.3V VOH VO L tPLZ 3.5V 0V
0V
ENABLE AND DISABLE TIMES
TEST CIRCUIT 1 is used for output enable/disable parameters. TEST CIRCUIT 2 is used for all other timing parameters.
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QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
AC TIMING DIAGRAM
S YN C
tPD FEEDBACK tJ Q tSKF Q0-Q4 tSKR Q /2
2xQ t SKA LL Q5
NOTES: 1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = VDD, the negative edge of FEEDBACK aligns with the negative edge of SYNC input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC. 2. All parameters are measured at 1.5V.
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QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5919T provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency multiplying or inversion is performed by digital logic following the PLL (see the block diagram). The key advantage of the PLL circuit is to provide an effective zero propagation delay between the output and input signals. In fact, adding delay circuits in the feedback path, `propagation delay' can even be negative! A simplified schematic of the QS5919T PLL circuit is shown below.
SIMPLIFIED DIAGRAM OF QS5919T FEEDBACK
2xQ
Q
Q
Q /2
INPU T PHASE DETECTOR
VCO
/2
/2
The phase difference between the output and the input frequencies feeds the VCO which drives the outputs. Whichever output is fed back, it will stabilize at the same frequency as the input. Hence, this is a true negative feedback closed loop system. In most applications, the output will optimally have zero phase shift with respect to the input. In fact, the internal loop filter on the QS5919T typically provides within 150ps of phase shift between input and output.
If the user wishes to vary the phase difference (typically to compensate for backplane delays), this is most easily accomplished by adding delay circuits to the feedback path. The respective output used for feedback will be advanced by the amount of delay in the feedback path. All other outputs will retain their proper relationships to that output.
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QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
QS XXXX Device Type XX Speed X Package
Q J
Quarter Size Outline Package (SO28-9) Plastic Leaded Chip Carrier (J28-1)
55 70 100 133 160
55MHz Max. Frequency 70MHz Max. Frequency 100MHz Max. Frequency 133MHz Max. Frequency 160MHz Max. Frequency
5919T
Low Skew TTL PLL Clock Driver with Integrated Loop Filter
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